In modern communication receiver, the received signal is quantized by an analog-to-digital converter (ADC) so that complex signal processing can be performed in the digital domain. A delta-sigma modulator is commonly used. It can be easily realized using low-cost CMOS processes, such as the processes used to produce digital integrated circuits. However, an input signal is usually very faint. Therefore, gain amplifiers are used to provide proper inputs for a better performance of the modulator.
A gain amplifier being able to amplify a wide dynamic range of analog input signals is desired. Multiple stage programmable gain amplifiers were invented for this purpose. Take a high gain 2-stage operational amplifier for example. It will have bandwidth up to 3 dB. According to different specific feedback factor and phase margin in a closed-loop configuration, the design of wide range programmable gain amplifiers is very difficult to keep stable for ‘wide range’. Another problem usually met in use of ADC is noise. For higher resolution ADC, the error source comes from noise. For lower resolution ADC, the major noise is flicker noise of the operational amplifier. Meanwhile, an offset voltage always exists due to mismatch of the circuit design. Power consumption is also disproportionate in multiple stage amplifiers. Many inventions were invented to solve or eliminate these problems.
Please see FIG. 1. U.S. Pat. No. 4,438,354 provides a solution to eliminate the inherent offset voltages of the operational amplifiers contained within the circuit. Offset voltages from other causes, including parasitic capacitances, switch operation, and leakage currents are also eliminated.
FIG. 2 shows invention of U.S. Pat. No. 4,555,668. The gain amplifier reduces offset voltage by delaying the phase of clock in the second stage. Two gain stages reduce the total capacitance ratio between input capacitors and feedback capacitor to achieve a desired total gain.
U.S. Pat. No. 6,661,283 illustrated in FIG. 3 is a single stage programmable gain amplifier. The '283 patent has advantages to reduce power dissipation and thermal noise.
U.S. Pat. No. 6,262,626 shown in FIG. 4 and U.S. Pat. No. 7,224,216 shown in FIG. 5 utilize chopper technique. Usually, chopping techniques for amplifiers have been utilized to modulate the offset and the 1/f noise to higher frequency. With low pass filter, the offset and the 1/f noise can be ideally removed. The '626 patent uses a pair of choppers to reduce the DC-offset and noise caused by amplifier. The '216 patent uses at least two chopping amplifier stages. The effect of the '216 patent can resolve open loop problem, avoid the runaway situation, and reduce aliasing of noise to the frequency baseband and the magnitude of chopping artifacts.
Although these inventions solve some of the problems mentioned above, there is no one able to have a total solution.